The present invention relates generally to microprocessors, and more particularly to an arithmetic logic unit of a microprocessor.
As used herein the term "byte" shall refer to an 8-bit digital word where the least significant bit is "bit 0" and the most significant bit is "bit 7" with intervening bits named accordingly. The term "word" shall refer to two bytes, a series of sixteen bits from "bit 0" to "bit 15" with intervening bits named accordingly. When applying logical operations to digital values the symbol "*" shall represent an AND function, the symbol "+" shall represent an OR function, and the prefix "!" shall represent inversion.
Some instruction opcodes in microprocessor instruction sets contain a sign extension bit for converting a signed byte operand into a signed word operand. For example, the iAPX 86 family of microprocessors includes opcodes with sign extend bits. In the prior art, this has been accomplished by physically replicating the sign bit of the byte operand into the second byte of the word operand. Thus, bit 7 of the byte operand becomes bits 8 through 15 of the word operand and the word operand is then applied in some fashion to an arithmetic or logical function. Such physical replication of the sign bit into the upper or second byte of the word operand requires a separate machine cycle in response to an opcode having the sign extend bit set.
U.S. Pat. No. 4,363,091 entitled EXTENDED ADDRESS, SINGLE AND MULTIPLE BIT MICROPROCESSOR, filed Jan. 31, 1978 by Pohlman, III et al., and issued Dec. 7, 1982, shows an implementation of sign bit extension within a microprocessor.
It is desirable to provide the same ultimate result as achieved by sign bit extension in response to opcodes presented to a microprocessor, without requiring a separate machine cycle to accomplish sign bit extension. The subject matter of the present invention provides a mechanism for achieving this result in a microprocessor.